? semiconductor components industries, llc, 2015 july, 2015 ? rev. 3 1 publication order number: nlas1053/d nlas1053 2:1 mux/demux analog switches the nlas1053 is an advanced cmos analog switch fabricated with silicon gate cmos technology. it achieves very high speed propagation delays and low on resistances while maintaining cmos low power dissipation. the device consists of a single 2:1 mux/demux (spdt), similar to on semiconductor?s nlas4053 analog and digital voltages that may vary across the full power supply range (from v cc to gnd). the inhibit and select input pins have over voltage protection that allows voltages above v cc up to 7.0 v to be present without damage or disruption of operation of the part, regardless of the operating voltage. features ? high speed: t pd = 1 ns (typ) at v cc = 5.0 v ? low power dissipation: i cc = 2 a (max) at t a = 25 c ? high bandwidth, improved linearity, and low rds on ? inh pin allows a both channels ?off? condition (with a high) ? rds on ? 25 , performance very similar to the nlas4053 ? break before make circuitry, prevents inadvertent shorts ? useful for switching video frequencies beyond 50 mhz ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; mm > 200 v, cdm > 1500 v ? tiny us8 package, only 2.1 x 3.0 mm ? these devices are pb?free, halogen free/bfr free and are rohs compliant ch0 inh 8 1 2 3 7 6 ch1 select gnd n/c figure 1. pin assignment 4 5 v cc com www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. device package shipping ? ordering information NLAS1053USG us8 (pb?free) 3000 / tape & ree l marking diagram us8 us suffix case 493 8 1 1 8 ac m ac = specific device code m = date code = pb?free package (note: microdot may be in either location) function table h l l inh x l h select off ch 0 off off ch 1 on off on
nlas1053 www. onsemi.com 2 maximum ratings parameter symbol value unit positive dc supply voltage v cc ? 0.5 to + 7.0 v digital input voltage (select and inhibit) v in ? 0.5 v is + 7.0 v analog output voltage (v ch or v com ) v is ? 0.5 v is v cc + 0.5 v dc current, into or out of any pin i ik 50 ma storage temperature range t stg ? 65 to + 150 c lead temperature, 1 mm from case for 10 seconds t l 260 c junction temperature under bias t j + 150 c thermal resistance ja 250 c/w power dissipation in still air at 85 c p d 250 mw moisture sensitivity msl level 1 flammability rating oxygen index: 30% ? 35% f r ul 94 v?0 @ 0.125 in esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) v esd > 2000 200 n/a v latchup performance above v cc and below gnd at 85 c (note 5) i latchup 300 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. measured with minimum pad spacing on an fr4 board, using 10 mm?by?1 inch, 2?ounce copper trace with no air flow. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. 5. tested to eia/jesd78. recommended operating conditions characteristics symbol min max unit positive dc supply voltage v cc 2.0 5.5 v digital input voltage (select and inhibit) v in gnd 5.5 v static or dynamic voltage across an off switch v io gnd v cc v analog input voltage (ch, com) v is gnd v cc v operating temperature range, all package types t a ? 55 + 125 c input rise or fall time v cc = 3.3 v 0.3 v (enable input) v cc = 5.0 v 0.5 v t r , t f 0 0 100 20 ns/v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 normalized failure rate 1 1 10 100 1000 time, years failure rate of plastic = ceramic until intermetallics occur figure 2. failure rate versus time junction temperature t j = 130 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c t j = 120 c
nlas1053 www. onsemi.com 3 dc characteristics ? digital section (voltages referenced to gnd) parameter condition symbol v cc guaranteed limit unit 55 c to 25 c 85 c 125 c minimum high?level input voltage, select and inhibit inputs v ih 2.0 2.5 3.0 4.5 5.5 1.5 1.9 2.1 3.15 3.85 1.5 1.9 2.1 3.15 3.85 1.5 1.9 2.1 3.15 3.85 v maximum low?level input voltage, select and inhibit inputs v il 2.0 2.5 3.0 4.5 5.5 0.5 0.6 0.9 1.35 1.65 0.5 0.6 0.9 1.35 1.65 0.5 0.6 0.9 1.35 1.65 v maximum input leakage current, select and inhibit inputs v in = 5.5 v or gnd i in 0 v to 5.5 v 0.1 1.0 1.0 a maximum quiescent supply current select and inhibit = v cc or gnd i cc 5.5 1.0 1.0 2.0 a dc electrical characteristics ? analog section parameter condition symbol v cc guaranteed limit unit 55 to 25 c 85 c 125 c maximum ?on? resistance (figures 17 ? 23) v in = v il or v ih v is = gnd to v cc i in i 10.0 ma r on 2.5 3.0 4.5 5.5 70 40 20 16 85 46 28 22 105 52 34 28 on resistance flatness (figures 17 ? 23) v in = v il or v ih i in i 10.0 ma v is = 1v, 2v, 3.5v r flat (on) 4.5 4 4 5 on resistance match between channels v in = v il or v ih i in i 10.0 ma v ch1 or v ch0 = 3.5 v r on (on) 4.5 2 2 3 ch1 or ch0 off leakage current (figure 9) v in = v il or v ih v ch1 or v ch0 = 1.0 v com 4.5 v i ch0 i ch1 5.5 1 10 100 na com on leakage current (figure 9) v in = v il or v ih v ch1 1.0 v or 4.5 v with v ch0 floating or v ch1 1.0 v or 4.5 v with v ch1 floating v com = 1.0 v or 4.5 v i com(on) 5.5 1 10 100 na
nlas1053 www. onsemi.com 4 ac electrical characteristics (input t r = t f = 3.0 ns) parameter test conditions symbol v cc (v) guaranteed max limit unit 55 to 25 c 85 c 125 c min typ* max min max min max turn?on time (figures 12 and 13) inh to output r l = 300 c l = 35 pf (figures 4 and 5) t on 2.5 3.0 4.5 5.5 2 2 1 1 7 5 4 3 12 10 9 8 2 2 1 1 15 15 12 12 2 2 1 1 15 15 12 12 ns turn?off time (figures 12 and 13) inh to output r l = 300 c l = 35 pf (figures 4 and 5) t off 2.5 3.0 4.5 5.5 2 2 1 1 7 5 4 3 12 10 9 8 2 2 1 1 15 15 12 12 2 2 1 1 15 15 12 12 ns transition time (channel selec- tion time) (figure ) select to output r l = 300 c l = 35 pf (figures and ) t trans 2.5 3.0 4.5 5.5 5 5 2 2 18 13 12 9 28 21 16 14 5 5 2 2 30 25 20 20 5 5 2 2 30 25 20 20 ns minimum break?before?make time v is = 3.0 v (figure 3) r l = 300 c l = 35 pf t bbm 2.5 3.0 4.5 5.5 1 1 1 1 12 11 6 5 1 1 1 1 1 1 1 1 ns typical @ 25, vcc = 5.0 v maximum input capacitance, select/inh input analog i/o (switch off) common i/o (switch off) feedthrough (switch on) c in c no or c nc c com c (on) 8 10 10 20 pf *typical characteristics are at 25 c. additional application characteristics (voltages referenced to gnd unless noted) parameter condition ???? ???? ???? c maximum on?channel ?3db bandwidth or minimum frequency response (figure 10) v in = 0 dbm v in centered between v cc and gnd (figure 7) ???? ???? ???? 0 dbm @ 100 khz to 50 mhz v in centered between v cc and gnd (figure 7) ???? ???? ???? ???? ? 3 ? 3 ? 3 db off?channel isolation (figure 10) f = 100 khz; v is = 1 v rms v in centered between v cc and gnd (figure 7) ???? ???? ???? ? 93 ? 93 ? 93 db charge injection select input to common i/o (figure 15) v in = v cc to gnd, f is = 20 khz t r = t f = 3 ns r is = 0 , c l = 1000 pf q = c l * v out (figure 8) ???? ???? ???? ???? c l = 50 pf v is = 5.0 v pp sine wave ???? ???? ????
nlas1053 www. onsemi.com 5 50% 50% 10 % 10% 0 v input output 35 pf input open output dut 50% 50% 0 v input output 90% 90% input open 35 pf 300 output dut 90% gnd output gnd input 35 pf switch select pin output dut figure 3. t bbm (time break?before?make) 300 v cc v cc 90% of v oh figure 4. t on /t off t on t off v oh v cc figure 5. t on /t off v cc t on t off v cc 300 0.1 f t bmm v out v ol v out v oh v ol v cc v out 0.1 f inh inh
nlas1053 www. onsemi.com 6 output 0 v input 50% 50% 90% 10% select pin output 35 pf figure 6. t trans (channel selection time) 300 v cc v cc 0.1 f v out gnd gnd v cc t trans t trans channel switch control/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3 db below v onl output dut input 50 50 generator reference transmitted figure 7. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl 50 v out v in v out v in off on off v out v cc gnd output v in c l dut figure 8. charge injection: (q) v in open output
nlas1053 www. onsemi.com 7 ?55 ?20 leakage (na) figure 9. switch leakage versus temperature 1 i ch(off) temperature ( c) 0.01 25 0.001 0.1 70 85 125 i com(on) i com(off) v cc = 5.0 v 10 100 figure 10. bandwidth and off?channel isolation 0.01 10 1 0.1 (db) ?100 0 off isolation frequency (mhz) 100 20 0 ?80 ?60 ?40 ?20 bandwidth (on?response) v cc = 5.0 v t a = 25 c 10 30 20 frequency (mhz) figure 11. phase versus frequency 0.01 0.1 100 1 10 200 0 v cc = 5.0 v t a = 25 c phase (degree) 2.5 4.5 35 figure 12. t on and t off versus v cc at 25 c v cc (volts) time (ns) t trans (ns) t on /t off (ns) 3.5 4 30 20 15 25 0 10 5 30 figure 13. t on and t off versus temp temperature ( c) time (ns) ?55 25 125 ?40 20 15 25 0 t trans 10 5 t on /t off v cc = 4.5 v 85 1 0.1 0.01 figure 14. total harmonic distortion plus noise versus frequency frequency (khz) thd + noise (%) 10 1 100 v inpp = 5.0 v v cc = 5.5 v v inpp = 3.0 v v cc = 3.6 v
nlas1053 www. onsemi.com 8 3. 5 2 1.5 1 0.5 0 0 15 25 35 40 ron ( ) v com (volts) 30 20 10 2.5 85 c ?55 c 125 c 25 c 5 3 3 2 1.5 1 0.5 0 0 20 40 60 70 ron ( ) v com (volts) 50 30 10 2.5 85 c ?55 c 125 c 25 c 2. 5 2 1.5 1 0.5 0 0 20 40 60 80 100 ron ( ) v com (volts) 90 70 50 30 10 5 4 3 2 1 0 0 20 40 60 80 100 ron ( ) v com (volts) v cc = 4.5 v v cc = 3.0 v v cc = 2.0 v v cc = 2.5 v 3.0 figure 15. charge injection versus com voltage v com (v) q (pc) 034 2 15 v cc = 3 v v cc = 5 v 2.5 2.0 1.5 1.0 0.5 0 ?0.5 temperature ( c) figure 16. i cc versus temp, v cc = 3 v & 5 v i cc (na) figure 17. r on versus v com and v cc (@ 25 c figure 18. r on versus v com and temperature, v cc 2.0 v figure 19. r on versus v com and temperature, v cc = 2.5 v ?40 60 80 20 0 100 ?20 120 v cc = 3.0 v v cc = 5.0 v 10 1 0.1 100 0.01 0.001 0.0001 0.00001 figure 20. r on versus v com and temperature, v cc = 3.0 v 85 c ?55 c 125 c 25 c
nlas1053 www. onsemi.com 9 6 2 1 0 0 20 ron ( ) v com (volts) 10 345 85 c ?55 c 125 c 25 c 15 5 6 2 1 0 0 16 18 ron ( ) v com (volts) 14 10 12 8 6 4 2 345 85 c ?55 c 125 c 25 c 5 4 3 2 1 0 0 4 8 12 16 20 ron ( ) v com (volts) 18 14 10 6 2 85 c ?55 c 125 c 25 c figure 21. r on versus v com and temperature, v cc = 4.5 v figure 22. r on versus v com and temperature, v cc = 5.0 v figure 23. r on versus v com and temperature, v cc = 5.5 v
nlas1053 www. onsemi.com 10 package dimensions us8 us suffix case 493?02 issue d 0.30 8x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 recommended 1 pitch 3.40 0.68 8x dim a min max min max inches 1.90 2.10 0.075 0.083 millimeters b 2.20 2.40 0.087 0.094 c 0.60 0.90 0.024 0.035 d 0.17 0.25 0.007 0.010 f 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.40 ref 0.016 ref j 0.10 0.18 0.004 0.007 k 0.00 0.10 0.000 0.004 l 3.00 3.20 0.118 0.128 m 0 6 0 6 n 0 10 0 10 p 0.23 0.34 0.010 0.013 r 0.23 0.33 0.009 0.013 s 0.37 0.47 0.015 0.019 u 0.60 0.80 0.024 0.031 v 0.12 bsc 0.005 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension a does not include mold flash, protrusion or gate burr. mold flash. protrusion and gate burr shall not exceed 0.14mm (0.0055?) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash and protrusion shall not exceed 0.14mm (0.0055?) per side. 5. lead finish is solder plating with thickness of 0.0076?0.0203mm (0.003?0.008?). 6. all tolerance unless otherwise specified 0.0508mm (0.0002?). l b a p g 4 1 5 8 c k d seating j s r u detail e v f h n r 0.10 typ m detail e t m 0.10 (0.004) xy t 0.10 (0.004) plane x y t p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nlas1053/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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